Verilog XL Simulation


In this tutorial you will simulate your 2:1 multiplexor from the previous tutorial.  The tutorial details every step of the process.  You should follow every step exactly as outlined.  After completing the tutorial you may want to play around with the simulator in order to become more familiar with it.

Preparing for Simulation

Open the 2:1 multiplexor schematic you created in the previous tutorial.  Do this by launching icfb, clicking on your library in the Library Manager, clicking on the 2:1 mux cell and double clicking the schematic view.  The schematic window should open up with your mux displayed in it.

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Simulation, 2:1 Multiplexor

Cadence offers numerous simulation techniques.  For now, we're just going to do a digital behavioral simulation to make sure the multiplexor is logically correct.

In the schematic composer window select Tools -> Simulation -> Verilog-XL.  The Setup Environment form will open up.  It is automatically filled out based on the schematic window you used to open Verilog-XL so you should already see your library, mux2_1 and schematic in the appropriate boxes.  If you don't, use the library browser button to find your mux2_1 schematic.

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Press OK.  The Verilog-XL Integration form opens up.  The next step in your simulation is to write a simulation file.  Cadence automatically creates a template file for you, but you need to fill in the guts.  Here are the steps to get to the template file:

Select Stimulus -> Verilog...

Agree to creating a test fixture for your design by pressing Yes on the dialog box

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This opens the Stimulus Options form.

Change the mode to Copy by pressing the appropriate radio button.  Select testfixture.verilog from the scrollbox under file name.  Select Make Current Test Fixture and Check Verilog Syntax at the bottom of the form.  All the other information defaults to correct values.

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Press Apply to make the copy.  Notice that the Copy To file name is

Set the mode to Edit by selecting the correct radio button.

Make sure that file name is

Press Apply, emacs (or whatever you set your default editor to) should open the file.  The text will look like this:

// Verilog stimulus file.

// Please do not create a module in this file.

// Default verilog stimulus.



   A = 1'b0;

   B = 1'b0;

   Sel = 1'b0;


Modify the file to match the following text.  These commands will simulate your design.

// Verilog stimulus file.

// Please do not create a module in this file.

// Default verilog stimulus.



   A = 1'b0;        // A = 1 bit wide value 0

   B = 1'b0;        // B = 1 bit wide value 0

   Sel = 1'b0;      // Sel = 1 bit wide value 0

   #10 A = 1'b1;    // run 10 ns then set A = 1 bit wide value 1

   #10 Sel = 1'b1;  // run 10 ns then set Sel = 1 bit wide value 1

   #10 B = 1'b1;    // run 10 ns then set B = 1 bit wide value 1

   A = 1'b0;        // set A = 1 bit wide value 0

   #10 Sel = 1'b0;  // run 10 ns then set Sel = 1 bit wide value 0

   #10 $finish;     // run 10 ns and finish (finish is required!)


// monitor some signals so the output is sent to the command window


   $monitor( $time, "  A = %b, B = %b, Sel = %b, Out = %b", A, B, Sel, Out );

Go ahead and close your editor.  Set the mode of the Stimulus Options form to Select by clicking on the appropriate radio button.  Make sure is selected in filename and press OK.  The form should close and you are looking at the Verilog-XL Integration form.

Select Simulation -> Start Interactive or press the upper left hand button on the toolbar.  This compiles your testfixture file and gives you some feedback.  There should not be any errors or warnings in the command window.  If there are, read them and find out what syntax errors you had in your testfixture.  Open the testfixture for editing again and fix your mistakes.  Try the Start Interactive command again.  Repeat this process until you get the following output.

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Select Simulation -> Continue or press the play button on the toolbar.  The simulation completes and displays the output of the $monitor statement in the command window.

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You can verify that the 2:1 mux works correctly from just this output, but there is a better way to look at the results.  The lower right hand button on the toolbar lets you view waveforms.  Press it now.  This opens a tool called SimVision.  Alternatively you could select Debug -> Utilities -> View Waveform... to open the same window.

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SimVision is a waveform viewer.  It allows you to view your simulation signals in a graphical format rather than a textual format.

To display the mux simulation waveforms choose Windows -> New Design Browser or click on the toolbar button AbiWord Image mux2_1_simulation07_designbrowserbtn.png .  This opens the design browser window from which you will choose which waveforms to display.  Expand the test view and click on top.  You should now see all the signals in your simulation (A, B, Sel and Out) in the right hand window.  Highlight all of them.

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Right click on the selected signals and choose Send to target Waveform Window or click on AbiWord Image mux2_1_simulation09_sendtowaveformbtn.png to send the waveforms back to the main SimVision window.  It should now look like this:

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Verify that when Sel is low, A is reflected at the Output and when Sel is high, B is reflected at the output.  Play around with the zoom and fit to screen features so that you are familiar with their use.  Fiddle with any other features of the simulator you think might come in handy in the future.  The more familiar you are with the simulation environment, the easier future labs will be to complete.


Good job.  You have successfully designed and simulated a 2:1 multiplexor.  The next tutorial teaches you how to use hierarchy in Cadence to build a 4:1 mux out of the 2:1 mux.