An extremely powerful concept in VLSI is the standard cell library. Standard cells help create efficient dense layouts because they are easily abutted during the layout process. Standard cell layout simply means that all standard cells - nand, nor, not, etc. - in the design are layed out with standard dimensions for heights, widths, actives and wells, and have standard power (vdd!) and ground (gnd!) busses.
The main purpose of this tutorial is to you how to use Virtuoso Layout Editor and create a layout of an inverter that could be used in a standard cell library. The tutorial also includes instructions on checking (DRC and LVS) the layout.
It is much easier to ensure that your standard cell library is actually standard by creating a standard cell template which you copy into your individual cell layouts. All the standard cells in your library will have a fixed height. We're going to set it at 90 lambda (54 microns: remember a 1.2 micron process has a lambda of 0.6u). They will all have a minimum width, but can be wider depending on the size of a cell. For instance, inverters are very narrow, nand gates are somewhat wider, and flip-flops are much wider. When you need wider cells, simply abut multiple standard cell templates together.
Fire up cadence (icfb) and create a library following the instructions in Cadence Setup: For the first-time user. In the Library Window, select the library you have created and then select File -> New -> Cellview... Make sure the Cell Name field reads "template" and type "layout" in the View Name field. After typing "layout", hit TAB and the Tool should automatically change to Virtuoso. If it doesn't, then manually change it by selecting the drop down box. Select OK and the Virtuoso Layout Editing Window will open, along with the Layer Select Window (LSW). The LSW contains all of the different layers needed for the layout process. (You will only need to use some of these layers. Note: in the following picture, a different technology library has been used, and thus the layers are not quite the same as you will see.)
The Virtuoso Layout Editing Tool has similar side
icons to those of the Virtuoso Schematic Editing Tool.
Some of the ones that will be used frequently in this
tutorial are the rectangle icon (or typing 'r') and
the ruler icon (or typing 'k'). The other icons are
pretty straight forward to understand and will be
referred to if they are needed.
Use the ruler to measure out an area 54 u tall and 10.2 u wide. Use the 0,0 origin as your starting reference point. Your layout view should look like the picture.
Make a power bus at the top of the cell. Use metal1 to draw a rectangle 4.8 u by 15 u. (The 'r' key selects rectangle drawing.) Notice how it hangs over the edges of the area we defined with the ruler? This is so the cells adjoin easily later on. It should hang 2.4 u over the edge.
Copy the metal one rectangle and place the copy at the bottom of the cell. This is your ground bus. Make sure it also hangs over the cell area you defined the same way the power bus does.
Because the vdd and gnd busses will be embedded in nwells and pwells, we need to put nselect and pselect around them. Put an nselect region around the vdd bus. Make it 0.3 u larger on every side than the metal1 rectangle. Put a similar pselect region around the gnd bus.
Generally the pullup devices are larger than their corresponding pulldown devices. Planning for this, draw your n-select and p-select regions. Make the pselect region take up about 2/3 of the cell. Draw a pselect rectangle 26.7 u high by 10.2 u wide. Butt it up against the nselect around the vdd bus. Draw an nselect rectangle 17.1 u by 10.2 u. Butt it up against the pselect around the gnd bus. Note, it will help you to watch the delta X and delta Y coordinates at the top of your screen while drawing rectangles.
Create the pwell and the nwell. The nwell goes around the p-type transistors and the pwell goes around the n-type transistors. The wells should extend 0.3 u around the p and n select boxes surrounding the vdd and gnd busses. They should meet exactly between the p and n select boxes in the body of the cell.
Create contacts to connect the vdd and gnd busses. This helps avert latchup. To create contacts press 'o' and select M1 to Active. Place three contacts on the vdd bus and three on the gnd bus. Make sure they are placed exactly at (0, 0), (5.1, 0), (10.2, 0), (0, 54), (5.1, 54) and (10.2, 54).
In order to see what is inside the contacts, press 'e' to bring up the display options and set the display level to 10. Display levels are referring to the layers on the chip layout but refer to levels of detail. What we are doing here is logically looking at details about our pins that relate back to the schematic.
Whenever you make edits to a layout, you need to ensure that no layout design rules have been violated. The tools help you with this by providing a "Design Rule Check" (DRC) tool. To run DRC, save your layout and then select Verify -> DRC...
Make sure that the "Rules File" field contains "divaDRC.rul". This is the file that contains all of the design rules that the layout must adhere to. Make sure that the "Rules Library" field contains "AMI12". (NOTE: the picture below does not have the right "Rules Library" field.) You do not need to worry about changing any of the other options. Select OK. Then, check the CIW to make sure there were no errors. If there were any errors, the locations of errors will be highlighted in the Virtuoso Layout Editing window (you will see white lines, boxes, or crosses). Also, in the CIW, it will tell you the design rules that have been violated.
You can use the Verify -> Markers -> Find... command from the menu to make it easier to find violations. This command brings up a dialog box which you can use to "step" through the violations, highlighting or zooming into each one. Simply use the "Next" and "Previous" button to move through the violations.
Continue to edit the layout and fix violations until there are no remaining violations.
Now lets use the standard cell template created in the previous section to add an inverter to the standard cell library.
Create a schematic for an inverter following the instructions in Cell-level schematic entry. Call the cell "inv".
Create a new cellview called "inv" but this time choose layout for the cell type. Also open up the standard cell template layout. Select the entire template, press 'c' to open the copy dialog, click somewhere in the template and them move the mouse over to the inverter layout window. Place the template in the inverter layout. Carefully place the lower left contact right on the origin. Remember, in order for the standard cells to abut correctly they need to share a common origin.
Odds are the contacts do not look right. Press 'e' to open the display options and set Display Level Stop to 2.
Draw the inverter making sure it matches the pictures below and that the transistor widths are correct.
The inverter pullup: Draw a box of active 7.8 u by 10.8 u. Place a bar of poly 1.2 u wide. It should overlap the active by 1.2 u. Press 'o' to open the contacts menu. Select metal1 to active contacts, 1 column, 4 rows and place them as shown. Make a small rectangle of metal1 to connect the left side contacts to the vdd bus. Note: running DRC at this point is a good idea. It should pass easily. If it doesn't, make sure all the layers are sized correctly and try again.
The inverter pulldown: Draw a box of active 7.8 u by 3.6 u. Stretch the bar of poly from the pullup section down to the pulldown section. Make sure it overlaps the active by 1.2 u. Press 'o' to open the contacts menu. Select metal1 to active contact, 1 column, 1 rows and place two of them as shown. Make a small rectangle of metal1 to connect the left side contacts to the gnd bus. Note: The layout should pass DRC at this point.
The contacts: Placing contacts in standard cells is easy. The only things you need to think about are routing lanes. You want to be able to route horizontal tracks of metal 2 over your standard cells. Parallel metal 2 paths must be separated by 2.4 u. That means you can theoretically have a metal 2 path every 4.2 u - that is, 2.4 u between paths and the paths are 1.8 u wide. Our cells have routing tracks every 6 u. This gives us a little extra room to manuver if we need it.
Start on the x-axis and draw a ruler up the right hand side of the inverter. See the figure below. Place your output contact at 27 u or 21 u. Place your input contact at 15 u. The input and output contacts are metal 1 to metal 2 vias. In order to hook the input contact up the the poly, place a metal 1 to poly contact next to the poly, connect it with a small piece of poly and then connect it to the input contact with metal 1. The reason we didn't just stack this up is that the process doesn't allow stacked vias. Most newer processes do, this is just a quirk of the technology we are working with.
Your contacts should look like the figure below.
Naming pins: Place two metal 2 layer shape pins and two metal 2 layer shape pins. First, select metal 2 in the LSW. (LSW stands for layer select window, it is probably on the left side of the screen.) Go to Create -> Pins and open the create pins window. Select mode as shape pin and make sure rectangle is selected. Select Display Name. In the terminal names block, type A Y. Select I/O type as input. The create pin box should look like the figure.
Go to the layout and draw a rectangle directly over the metal 1 to metal 2 via on the input. Change I/O type to output and do the same for the output via. You should see something like the figure.
Now select metal 1 in the LSW. Create vdd and gnd shape pins on top of the gnd and vdd busses. Set the I/O type to inputoutput. Your finished inverter should look like the figure.
Now save and run DRC. Fix any violations you find.
If you close the layout view and reopen it, your pins may seem to disappear. They haven't; they've just become invisible. Open the display options by pressing 'e' and select "Pin Names" to make them visible again.
After you have completed a layout and it passes DRC, it is extremely important that you check that the layout you have created actually matches the schematic for the cell. The tools provide a "Layout vs. Schematic Check" (LVS) tool.
Before running, LVS, you must first "extract" the layout. To do this, select Verify -> Extract... in the Virtuoso Layout Editor window.
Leave all of the default settings and verify that the "Rules File" is "divaEXT.rul" and the "Rules Library" is "AMI12". Select OK. Verify that there are no errors in the CIW. A new "extracted" cell view has been created in your library. You can verify this by checking in the Library Manager Window.
To run LVS, select Verify -> LVS... in the Virtuoso Layout Editor window. The LVS dialog window will appear. Enter the library name and cell name in both the "schematic" and "extracted" area of the dialog box. Set the "View" to "schematic" and "extracted", respectively. (Note: be careful to check this every time you run LVS, particularly if you work on multiple cells.) Ensure that the "Rules File" is "divaLVS.rul" and the "Rules Library" is "AMI12". Make sure that all of the other options read like the image below. (Note: the image below has the wrong cell name and rules library.)
To check that the layout and schematic are the same, select Run. If the LVS succeeded, you should get a message saying so. This may take a minute or so to run.
This message means that LVS ran without crashing; it does not necessarily mean that there weren't any errors. In the LVS window, select Output to display the results of the check. If there weren't any errors, the output report should read "The netlists match". If the netlists didn't match, it may be because you used different names in the schematic from the names you used in the layout. There are other examples of why they won't match, but if you have followed this tutorial and the previous one, you shouldn't have any problems. (The output report can also be found in a file "si.out" in a subdirectory called "LVS" of the directory in which you invoked icfb. In general, all sorts of run files which can help debug LVS problems are in this subdirectory.)