Introduction

Writing in Verilog is very similar to writing in C. It is enough different that you can't simply sit down and type as though you are writing a C program. You need to learn the little peculiarities about Verilog in order to use it well. This tutorial does not try to teach you everything there is to know about Verilog programming. In fact, it will teach you very little. What it will do is point you at a couple of reference sites, show you a couple sample files and step you through the compilation and debug process. After that it is up to you to learn the language well enough to a) create your designs and b) prove to the professor that you understand what is going on.

Reference Sites

Below are some links to a few Verilog reference sites. Take a look at them and use the one(s) that you like best. The cadence reference is provided by cadence for use with their Verilog tools. It is the final language authority. You should definitely become familiar with it in addition to whichever other references you like.

• Cadence Verilog Reference - /ee2/Cadence/ldv/doc/vlogref/
vlogrefTOC.html
• Verilog HDL Quick Reference Guide
• Verilog Appendix

Search online for more references if these do not fullfill your needs. If you want to find a book on Verilog, look up Verilog HDL by Samir Palnitkar. It has some great examples and extensively explains the language.

Examples

This tutorial includes an example programs. It demonstrates a counter design. The files contains a couple different implementations of the same design to demonstrate various aspects of the language.

• Counter - Behavioral
• Counter - Functional

Open the code up in your favorite editor. (If it doesn't come up in verilog mode then you should download and install a verilog mode for your editor, note, you can use a c++ mode, it works pretty well for formating, it just doesn't highlight the correct keywords.) The comments explain what each line of code does.

To simply run the examples, type verilog <filename> into a terminal window. You should see some text output describing the circuit behavior.

The next section shows you how to use the graphical tools.

Compilation and Debug

Cadence provides a very nice tutorial explaining the NC tools. You'll need to work through it. It takes under an hour. Note: The tutorial references some example files. These are found in /ee2/Cadence/ldv/doc/ncvlogtut/examples.

• Cadence NCLaunch Tutorial - /ee2/Cadence/ldv/doc/ncvlogtut/
ncvlogtutTOC.html

Using the waveform viewer is also very well described in the same tutorial.

Just a note on some peculiarities. For some reason, the tools work better if you use the bash shell. When using csh, some students found that the nctools would not open correctly, they consistently could not find the necessary object files.

Conclusion

Nice job. You are ready to design a system in Verilog.