ECEn 451: Introduction to Digital VLSI Circuits

Winter 2011
Instructor: David A. Penry

(Click to see homework and lab assignments.)
Monday
Tuesday
Wednesday
Thursday
Friday
Jan 3 Jan 4 Jan 5: First class Jan 6 Jan 7
Jan 10: HW 1 Jan 11 Jan 12: HW 2 Jan 13 Jan 14: Lab 1
Jan 17: Holiday Jan 18 Jan 19: HW 3 Jan 20 Jan 21: Lab 2
Jan 24 Jan 25 Jan 26: HW 4 Jan 27 Jan 28
Jan 31: HW 5 Feb 1 Feb 2 Feb 3 Feb 4: HW 6
Feb 7 Feb 8 Feb 9 Feb 10 Feb 11: Lab 3
Feb 14: HW 7 Feb 15: Midterm 1 Feb 16: Midterm 1 Feb 17: Midterm 1 Feb 18: HW 8
Feb 21: Holiday Feb 22 (Monday class) Feb 23 Feb 24 Feb 25: HW 9
Feb 28: HW 10 Mar 1 Mar 2 Mar 3 Mar 4
Mar 7: HW 11 Mar 8 Mar 9 Mar 10 Mar 11: Lab 4
Mar 14: HW 12 Mar 15 Mar 16 Mar 17 Mar 18: Lab 5
Mar 21: Midterm 2 Mar 22: Midterm 2 Mar 23: Midterm 2 Mar 24 Mar 25:HW 13
Mar 28 Mar 29 Mar 30 Mar 31 Apr 1: Lab 6
Apr 4 Apr 5 Apr 6: HW 14 Apr 7 Apr 8
Apr 11: No class Apr 12 Apr 13: Lab 7 / Last class Apr 14: Reading day Apr 15: Reading day
Apr 18: Finals Apr 19: Finals Apr 20: Finals Apr 21: Finals/Graduation Apr 22: Graduation

Reading and Lecture Schedule

 You are expected to read the assigned sections before the class in which they are discussed.
 
 
 
 Date 
Topic 
Reading 
Wed Jan 5 Course introduction, static CMOS gates —
Thu Jan 6 Recitation: Cadence setup and schematic editor —
Fri Jan 8 Static CMOS gates 1.1 - 1.4.5

Mon Jan 10 Fabrication 1.5.1 - 1.5.2, 3.2
Wed Jan 12 Standard cells, Stick diagrams 1.5.3 - 1.5.5
Thu Jan 13 Recitation: Cadence layout —
Fri Jan 14 Size estimation; design rules 3.3, 3.5, 8.8

Mon Jan 17 Holiday: No class —
Wed Jan 19 Design flows and economics 1.6, 8.1, 8.3-8.5, 8.11
Thu Jan 20 Recitation: None —
Fri Jan 21 Voltage model and pass transistors 1.4.6 - 1.4.8

Mon Jan 24 CMOS device characteristics 2.1 - 2.2
Wed Jan 26 DC transfer 2.5
Thu Jan 27 Recitation: None —
Fri Jan 28 RC delay models 2.6, 4.1 - 4.2.2

Mon Jan 31 RC delay models, continued —
Wed Feb 2 Characterization 5.4 - 5.5
Thu Feb 3 Recitation: Cadence simulation tools —
Fri Feb 4 Logical effort: motivation and derivation 4.2.3 - 4.2.4, 4.3

Mon Feb 7 Logical effort: derivation and size optimization —
Wed Feb 9 Logical effort: path optimization 4.7, 5.4 - 5.5
Thu Feb 10 Recitation: midterm review —
Fri Feb 11 Logical effort: problems &mdash

Mon Feb 14 Static CMOS variants 6.2.1, 6.2.2, 6.2.5
Wed Feb 16 Static CMOS variants: problems and comparisons —
Thu Feb 17 Recitation: None —
Fri Feb 18 Pseudo-NMOS/Dynamic CMOS 6.2.3 - 6.2.4

Mon Feb 21 Holiday: No class —
Tue Feb 22 Dynamic CMOS —
Wed Feb 23 Domino logic —
Thu Feb 24 Recitation: None —
Fri Feb 25 Wire delays 4.5

Mon Feb 28 Wire engineering 4.6
Wed Mar 2 Noise 5.6
Thu Mar 3 Recitation: Cadence noise analysis tools —
Fri Mar 4 Scaling and MOS device model limitations 4.9

Mon Mar 7 Sequential element design 7.3
Wed Mar 9 Sequential element characterization and metastability 7.4.4, 7.6
Thu Mar 10 Recitation: Simulation for sequential element characterization —
Fri Mar 11 Sequential circuit timing 7.1 - 7.2

Mon Mar 14 Sequential circuit timing, cont. —
Wed Mar 16 Sequential circuit timing, cont. —
Thu Mar 17 Recitation: Midterm review —
Fri Mar 18 Sequential circuit timing, cont. —

Mon Mar 21 Array design and memory cells 11.2
Wed Mar 23 Power dissipation 4.4, 6.5
Thu Mar 24 Recitation: None —
Fri Mar 25 Power distribution 12.3

Mon Mar 28 Clock distribution 12.5
Wed Mar 30 Floorplanning / P&R 1.10
Thu Mar 31 Recitation: Cadence layout tools —
Fri Apr 1 I/O and packaging 12.2, 12.4

Mon Apr 4 Verification and Test Concepts 9.2 - 9.4
Wed Apr 6 Design for Test 9.5 - 9.7
Thu Apr 7 Recitation: None —
Fri Apr 8 Surprise topics —

Mon Apr 11 No class —
Wed Apr 13 Review —