ECEn 451: Introduction to Digital VLSI Circuits

Winter 2010
Instructor: David A. Penry

(Click to see homework and lab assignments.)
Monday
Tuesday
Wednesday
Thursday
Friday
Jan 4: First class Jan 5 Jan 6 Jan 7 Jan 8: HW 1
Jan 11: HW 2 Jan 12 Jan 13 Jan 14: Lab 1 Jan 15
Jan 18: Holiday Jan 19 Jan 20: HW 3 Jan 21 Jan 22: Lab 2
Jan 25 Jan 26 Jan 27: HW 4 Jan 28 Jan 29: no class
Feb 1: HW 5 Feb 2 Feb 3 Feb 4 Feb 5: HW 6
Feb 8 Feb 9 Feb 10 Feb 11: Lab 3 Feb 12: HW 7
Feb 15: Holiday Feb 16 (M class): Midterm 1 Feb 17: Midterm 1 Feb 18: Midterm 1 Feb 19
Feb 22: HW 8 Feb 23 Feb 24 Feb 25 Feb 26: HW 9
Mar 1: HW 10 Mar 2 Mar 3 Mar 4 Mar 5
Mar 8: HW 11 Mar 9 Mar 10 Mar 11 Mar 12: Lab 4
Mar 15: HW 12 Mar 16 Mar 17 Mar 18 Mar 19: Lab 5
Mar 22: Midterm 2 Mar 23: Midterm 2 Mar 24: Midterm 2 Mar 25 Mar 26:HW 13
Mar 29 Mar 30 Mar 31 Apr 1 Apr 2: Lab 6
Apr 5 Apr 6 Apr 7: HW 14 Apr 8 Apr 9
Apr 12: Lab 7 / Last class Apr 13 Apr 14: Reading day Apr 15: Reading day Apr 16: Finals
Apr 19: Finals Apr 20: Finals Apr 21: Finals Apr 22: Graduation Apr 23: Graduation

Reading and Lecture Schedule

 You are expected to read the assigned sections before the class in which they are discussed.
 
 
 
 Date 
Topic 
Reading 
Mon Jan 4 Course introduction, static CMOS gates —
Wed Jan 6 Static CMOS gates 1.1 - 1.4.5
Thu Jan 7 Recitation: Cadence setup and schematic editor —
Fri Jan 8 Fabrication 1.5.1 - 1.5.2, 3.2

Mon Jan 11 Standard cells, Stick diagrams 1.5.3 - 1.5.5
Wed Jan 13 Size estimation; design rules 3.3, 3.5, 8.8
Thu Jan 14 Recitation: Cadence layout —
Fri Jan 15 Design flows and economics 1.6, 8.1, 8.3-8.5, 8.11

Mon Jan 18 Holiday: No class —
Wed Jan 20 Voltage model and pass transistors 1.4.6 - 1.4.8
Thu Jan 21 Recitation: None —
Mon Jan 22 CMOS device characteristics 2.1 - 2.2

Mon Jan 25 DC transfer 2.5
Wed Jan 27 RC delay models 2.6, 4.1 - 4.2.2
Thu Jan 28 Recitation: None —
Fri Jan 29 No class —

Mon Feb 1 RC delay models, continued —
Wed Feb 3 Characterization 5.4 - 5.5
Thu Feb 4 Recitation: Cadence simulation tools —
Fri Feb 5 Logical effort: motivation and derivation 4.2.3 - 4.2.4, 4.3

Mon Feb 8 Logical effort: derivation and size optimization —
Wed Feb 10 Logical effort: path optimization 4.7, 5.4 - 5.5
Thu Feb 11 Recitation: midterm review —
Fri Feb 12 Logical effort: problems &mdash

Mon Feb 15 Holiday: No class —
Tue Feb 16 Static CMOS variants 6.2.1, 6.2.2, 6.2.5
Wed Feb 17 Static CMOS variants: problems and comparisons —
Thu Feb 18 Recitation: None —
Fri Feb 19 Pseudo-NMOS/Dynamic CMOS 6.2.3 - 6.2.4

Mon Feb 22 Dynamic CMOS —
Wed Feb 24 Domino logic —
Thu Feb 25 Recitation: None —
Fri Feb 26 Wire delays 4.5

Mon Mar 1 Wire engineering 4.6
Wed Mar 3 Noise 5.6
Thu Mar 4 Recitation: Cadence noise analysis tools —
Fri Mar 5 Scaling and MOS device model limitations 4.9

Mon Mar 8 Sequential element design 7.3
Wed Mar 10 Sequential element characterization and metastability 7.4.4, 7.6
Thu Mar 11 Recitation: Simulation for sequential element characterization —
Fri Mar 12 Sequential circuit timing 7.1 - 7.2

Mon Mar 15 Sequential circuit timing, cont. —
Wed Mar 17 Sequential circuit timing, cont. —
Thu Mar 18 Recitation: Midterm review —
Fri Mar 19 Sequential circuit timing, cont. —

Mon Mar 22 Array design and memory cells 11.2
Wed Mar 24 Power dissipation 4.4, 6.5
Thu Mar 25 Recitation: None —
Fri Mar 26 Power distribution 12.3

Mon Mar 29 Clock distribution 12.5
Wed Mar 31 Floorplanning / P&R 1.10
Thu Apr 1 Recitation: Cadence layout tools —
Fri Apr 2 I/O and packaging 12.2, 12.4

Mon Apr 5 Verification and Test Concepts 9.2 - 9.4
Wed Apr 7 Design for Test 9.5 - 9.7
Thu Apr 8 Recitation: None —
Fri Apr 9 Surprise topics —

Mon Apr 12 Review —